In time division multiplexed (TDM) communication systems, data is transmitted in a frame having a plurality of time slots. The data in each time slot is typically destined for separate receivers. The key to operating a TDM type of system is maintaining the proper timing of data in one time slot with respect to the frame and other time slots.
Presently, much of the timing operation is handled through the use of ASIC (Application Specific Integrated Circuits) devices. Their method of operation typically consists of receiving and storing the data to be transmitted in the various time slots. When a transmission frame begins, the ASIC will delay transmission of the data giving the receiver time to ramp up its power. This ramp up does not take long and the delay is only equivalent to a few bits. After the ramp up delay, a synchronization word is transmitted which will contain information such as the system identification (i.e. color code). Following the synchronization word, the first voice data is transmitted. At the end of the voice data, the ASIC delays a second data transmission to provide spacing between data in adjacent time slots. The process repeats itself for second, third, etc. time slots until the last time slot is reached. The frame will then repeat, if operating in a duplex configuration, or may be delayed for a receive cycle in a TDD (Time Division Duplex) system where transmit and receive occur on the same frequency.
Using the above means, the controller of the system is required to spend much of its processing ability in maintaining the timing of the transmission of data bits and retrieving the appropriate data bits at the desired time. Therefore, there is a need for a device which will free up processing functions and maintain the critical timing required to operate a TDM communication system.